The present invention relates generally to phase detection circuits, and, more particularly, to a digital phase discriminator.
Phase discriminators which respond to the phase difference between two signals have wide applications in wireless communication systems. For instance, in a fast switching phase-locked loop (PLL), the phase discriminator can be used to optimize the loop bandwidth. In the PLL, for minimizing noise, the loop bandwidth should be as narrow as possible. For fast channel switching and settling, the loop bandwidth needs to be large enough to facilitate the frequency switching. However, wider loop bandwidth results in poor reference spur cancellation. To accommodate these contradictory requirements in the PLL, a loop bandwidth booster is often used. During a frequency acquisition and tracking, where the PLL's output frequency and a reference frequency have a large difference, the loop bandwidth booster is turned on, so that the PLL has wider loop bandwidth. When the PLL's output frequency fall into a close range of the reference frequency, the loop bandwidth booster will be turned off.
The loop bandwidth booster control is conventionally realized by analogue circuits, such as using multiple phase-frequency-detectors and charge-pumps, or by a hybrid of analog and digital circuits. One problem with the conventional implementation is that they cannot distinguish phase differences between a reference signal and the PLL's output signal very precisely. Another problem, associated with the analogue circuits, is that when a process for manufacturing the PLL migrates to a different node, the loop bandwidth booster control circuit will be redesigned to be optimized for the new process.
As such, what is needed is a phase discriminator that can finely detect phase differences and is independent of process migrations. The phase discriminator can be used to control the aforementioned loop bandwidth booster as well as in many other applications.